A low noise 2.2 GHz PLL ASIC for the CSR external-target experiment

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作者信息关键词期刊信息会议信息基础信息归属信息摘要

成果类型：

期刊论文、会议论文

作者：

Hu, Z.;Gao, C.;Tian, X.;Zhu, P.;Liu, J.;...

作者机构：

[Gao, C.; You, B.; Yang, P.; Liu, X.; Wang, H.; Li, Y.; Qiao, Y.; Guo, D.; Chen, Q.; Huang, G.; Hu, Z.; Chen, K.; Sun, X.; Xiao, L.; Liu, J.; Liu, F.] Cent China Normal Univ, Key Lab Quark & Lepton Phys MOE, PLAC, Wuhan 430079, Hubei, Peoples R China.

[Tian, X.] Hubei Univ Sci & Technol, Sch Resources Environm Sci & Engn, Xianning 437100, Hubei, Peoples R China.

语种：

英文

关键词：

CMOS integrated circuits;Digital storage;Frequency allocation;Phase comparators;Phase noise;Timing circuits;Analog electronic circuit;Application-specific integrated circuits;CMOS readout of gaseous detector;Cooling storage ring;Design and tests;Detector readout;Front end;Front-end electronic for detector readout;Gaseous detectors;Lower noise;Phase locked loops

期刊：

Journal of Instrumentation

ISSN：

1748-0221

年：

2023

卷：

期：

页码：

C02011

会议名称：

Topical Workshop on Electronics for Particle Physics (TWEPP)

会议时间：

SEP 19-23, 2022

会议地点：

Bergen, NORWAY

会议主办单位：

[Hu, Z.;Gao, C.;Liu, J.;Wang, H.;Chen, K.;You, B.;Xiao, L.;Guo, D.;Yang, P.;Qiao, Y.;Li, Y.;Liu, X.;Chen, Q.;Sun, X.;Huang, G.;Liu, F.] Cent China Normal Univ, Key Lab Quark & Lepton Phys MOE, PLAC, Wuhan 430079, Hubei, Peoples R China.^[Tian, X.] Hubei Univ Sci & Technol, Sch Resources Environm Sci & Engn, Xianning 437100, Hubei, Peoples R China.

出版地：

TEMPLE CIRCUS, TEMPLE WAY, BRISTOL BS1 6BE, ENGLAND

出版者：

IOP Publishing Ltd

DOI：

10.1088/1748-0221/18/02/C02011

基金类别：

National Natural Science Foundation of China [12275105, 11927901, 12235006]

机构署名：

本校为第一机构

院系归属：

物理科学与技术学院

摘要：

Abstract This paper presents the design and test results of a low noise Phase Locked Loop (PLL) Application Specific Integrated Circuit (ASIC), which is designed for the data transmission system in a pixel chip for a beam monitor of the Cooling Storage Ring (CSR) external target experiment at HIRFL in China. The proposed PLL consists of a differential ring oscillator, a digital divider, a three-state phase frequency detector, a current charge pump, a second-order loop filter and current mode level buffers. A prototype PLL ASIC has been fabrica...

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A low noise 2.2 GHz PLL ASIC for the CSR external-target experiment

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