期刊论文

Research and design of self refresh check EDAC circuit based on SOI technology

中文

电子设计工程

1674-6236

2018

26

17

10-16

10.3969/j.issn.1674-6236.2018.17.003

国家自然科学基金面上项目（11375073）;国家自然科学基金重点项目（11220101005）； 国家重点研发计划科技部“高能环形正负电子对撞机相关的物理和关键技术预研究”（2016YFA0400400）；

本校为第一机构

对一种自刷新检纠错电路(EDAC)进行了研究与设计,并应用于单字节写操作SRAM中,提高了SRAM抗单粒子翻转效应(SEU)性能.EDAC采用hamming(12,8)编译码,实现"纠一检一"功能,数据宽度为32 bit的SRAM的EDAC由4组hamming(12,8)编译码电路组成,实现单字节操作,同时最多可纠4 bit错误.外围逻辑电路将EDAC电路纠错后的正确数据回写到SRAM对应的地址中,实现刷新功能,减少了SRAM的错误累积.同时,利用了Synopsys公司的EDA数字综合工具de-sign compiler和Cadence公司数字后端工具Encounter在130nm Silicon-On-Insulator(SOI)工艺上进行设计,并结合SRAM的verilog模型使用Cadence公司的仿真工具NClaunch仿真验证...

An Error Detection And Correction(EDAC)circuit with self-refresh function is studied and designed.The EDAC is used in a SRAM with single-byte writing operational function to improve its anti-SEU performance.Hamming(12,8)code realizing single error correction and single error detection is adopted for the EDAC.The EDAC for 32-bit SRAM is composed of four(12,8)hamming codes hence having correcting 4 bits capacity.Corrected data is written back into the corresponding memory by the periphery circuit.The EDAC is designed in 130nm Silicon-On-Insulator(SOI)process using the design compiler tool of Syn...